1. Field of the Invention
The present invention pertains to testing circuitry for flash memories, and to improvements in the time needed to screen flash memory arrays. More particularly, the present invention pertains to flash memory integrated circuits with on-board testing circuitry.
2. The Prior Art
It is well known that screening a flash array accounts for the majority of the time spent during flash memory testing. Flash array screening usually consists of a sequence of erasing the array, programming the array with a pattern, and reading and verifying the pattern written into the array. If the programmed pattern can be verified, then the array is assumed to be defect free, otherwise, if errors occur, some defects have been detected. Repeating the sequence with different patterns allows for the highlighting of different types of faults.
Thus, a key point in testing the array is determining whether or not the defects can be repaired by substituting a redundant row or column of the array, and calculating the redundancy information, which, once permanently stored in the device, will be used during the entire life cycle of the chip to substitute the faulty part of the array.
As technology features scale down and flash memory densities grow larger, the total number of interactions increase between the external tester and the flash memory during the array screening, becoming a real bottleneck. This is mainly due to the low frequency used to interface the flash memory with the external tester. Such low frequencies are needed to avoid bouncing and noise, because of the long cables connecting the probe card with the testing apparatus.
To deal with this issue, one of the testing strategies has been to embed on the chip all the logic and circuitry necessary for testing the array, thus reducing the number of interactions between the tester and the array. This strategy is also known as B.I.S.T. (Built-In Self Test).
Another common strategy to reduce test time has usually been to increase the number of dice tested in parallel. In this way, cost is shifted to expensive probe cards with larger buses for address and data, and complexity is transferred to longer software codes.